Cost Effective 2.3D Packaging Solution by using Fanout Panel Level RDL
Joonsung Kim, Jaehoon Choi, Sanguk Kim, Joo-Young Choi, Yongjin Park, Gyoungbum Kim, Sangyu Kim, Sang-Wook Park, Hwasub Oh, Seok Won Lee, Tae-Je Cho, Dongwook Kim
Abstract
The demand for high density and high performance package is increasing as AI and server market continues to grow. The demand for low cost packaging solution is stronger than ever, too. Conventional flip-chip ball grid array (FCBGA) package with multi-layered substrate (typically over 10 layers) suffers from the high cost of the substrate. The high cost of the substrate comes from the yield loss due to high layer count and large unit size. In this paper, we present the cost-effective packaging solution for high-performance server application, which consists of panel level package (PLP) interposer and conventional coarse pattern substrate. The basic concept is to divide the multi-layered FCBGA substrate into two substrates. One is the PLP interposer of fine pattern with fan-out panel level RDL technology, which is used for signal routing. The other is the coarse pattern substrate by low cost technology, which is used for power delivery. The partitioning of the FCBGA substrate works as a cost-effective solution because of the use of the low cost technology and higher total yield. We have demonstrated that the 10-layered FCBGA substrate could be partitioned into the 5-layered PLP interposer and the 8-layered coarse pattern substrate. In the assembly process, the PLP interposer was mounted on the coarse pattern substrate first and then the ASIC was assembled on the PLP interposer. The package warpage was within 100 um both at room temperature and high temperature. The simulation result of the return loss satisfied the characteristic criteria up to 28GHz.