GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network
Lihao Liu, Fan Yang, Li Shang, Xuan Zeng
Abstract
Interconnect capacitive parasitics are becoming increasingly dominant at finer technology nodes. Chip-scale interconnect capacitance extraction is a critical but challenging task. The structure patterns of nanometer-scale on-chip interconnects are complex. The accuracy of widely used pattern-matching-based capacitance extraction methods is limited by labor-intensive pattern library construction. This work presents graph neural network (GNN)-Cap, a GNN-based method for chip-scale interconnect capacitance extraction. GNN-Cap uses graph presentation learning to model the complex interconnect structural patterns, which enables accurate and efficient prediction of wiring capacitances. Compared with StarRC, the de facto commercial capacitance extraction tool, GNN-Cap achieves a speed up of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13\times $ </tex-math></inline-formula> , and reduces the average relative errors of total and coupling capacitances by 81% and 59%, respectively.