Half‐selection disturbance free 8T low leakage SRAM cell
Rohit Lorenzo, Roy Paily
Abstract
Summary This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.