Investigation of Fabricated CMOS FishboneFETs and TreeFETs With Strained SiGe Nano-Fins on Bulk-Si Substrate
Lei Cao, Qingzhu Zhang, Jiaxin Yao, Junjie Li, Yang Liu, Yanna Luo, Zhenzhen Kong, Na Zhou, Jianfeng Gao, Yihong Lu, Xiaobin He, Jianghao Han, Zhenhua Wu, Junfeng Li, Jun Luo, Huaxiang Yin
Abstract
Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed and experimentally fabricated. The growth of bottom SiGe layer with different Ge fraction following by an accurately selective etching is developed for realizing SiGe nano-fins between Si nanosheets (NSs). The results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}/{I}_{\text {off}}$ </tex-math></inline-formula> ratio (over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${1}\times {10} ^{{5}}{)}$ </tex-math></inline-formula> and the short channel effects (SCEs) of TreeFETs are effectively optimized, and the effective channel width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}_{\text {eff}}{)}$ </tex-math></inline-formula> is increased for FishboneFETs at the same footprint. Due to the hole conduction advantage of SiGe nano-fin, the on-current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}{)}$ </tex-math></inline-formula> of p-type TreeFETs can be higher than that of n-type TreeFETs at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OV}}=\vert V_{\text {gs}}$ </tex-math></inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\vert =0.5$ </tex-math></inline-formula> V. Meanwhile, the surface scattering of SiGe nano-fin also affects the effective field-effect mobility. As the gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {g}}$ </tex-math></inline-formula> ) scaling, both p-type tree-like FETs exhibit more obvious SCEs than n-type devices, which is maybe the reason of a lower hole barrier occurring by the valence band offset ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {E}_{\text {v}}{)}$ </tex-math></inline-formula> obtained in the strained SiGe nano-fin. The results provided one meaningful guide for tree-like FETs optimizing future GAAFET process and CMOS circuits.