High-Speed Modular Multiplier for Lattice-Based Cryptosystems
Weihang Tan, Benjamin M. Case, Antian Wang, Shuhong Gao, Yingjie Lao
Abstract
Thanks to the inherent post-quantum resistant properties, lattice-based cryptography has gained increasing attention in various cryptographic applications recently. To facilitate the practical deployment, efficient hardware architectures are demanded to accelerate the operations and reduce the computational resources, especially for the polynomial multiplication, which is the bottleneck of lattice-based cryptosystems. In this brief, we present a novel high-speed modular multiplier architecture for polynomial multiplication. The proposed architecture employs a divide and conquer strategy and exploits a special modulus to increase the parallelism and speed up the calculation, while enabling wider applications across various cryptosystems. The experimental results show that our design achieves around 27% and 39% reduction on the area consumption and delay, respectively, compared to prior works.