FPGA Implementation of A<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:msup><mml:mrow/><mml:mrow><mml:mi>∗</mml:mi></mml:mrow></mml:msup></mml:math> Algorithm for Real-Time Path Planning
Yuzhi Zhou, Xi Jin, Tianqi Wang
Abstract
The traditional A<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M2"><mml:msup><mml:mrow/><mml:mrow><mml:mi>∗</mml:mi></mml:mrow></mml:msup></mml:math> algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M3"><mml:msup><mml:mrow/><mml:mrow><mml:mi>∗</mml:mi></mml:mrow></mml:msup></mml:math> accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M4"><mml:msup><mml:mrow/><mml:mrow><mml:mi>∗</mml:mi></mml:mrow></mml:msup></mml:math> accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.