Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor
Tae Jun Yang, Jung Rae Cho, Hyunkyu Lee, Hee Jun Lee, Seung Joo Myoung, Da Yeon Lee, Sung‐Jin Choi, Jong‐Ho Bae, Dong Myong Kim, Changwook Kim, Jiyong Woo, Dae Hwan Kim
Abstract
Obtaining symmetrical and highly linear synapse weight update characteristics of analog resistive switching devices is critical for attaining high performance and energy efficiency of the neural network system. In this work, based on the two-terminal one transistor-one memristor (1T1M) block, the improvement of the symmetry and linearity of synaptic weight update is demonstrated by combining the InGaZnO synaptic transistor and memristor. Due to the symmetric and linear weight update characteristic, a pattern recognition accuracy of 88% is achieved after 50 epochs in the on-chip learning simulation of the hand-written digit images (MNIST) data set. The proposed 1T1M device saves the hardware burden and additional power consumption required to implement non-identical programming pulses.