High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets
Jing Guo, Shanshan Liu, Xiaohui Su, Chunhua Qi, Fabrizio Lombardi
Abstract
Latches areused extensivelyin digital circuits; however, as technology scaling reaches nanometric feature sizes, externally induced phenomena (such as radiation strikes in aerospace applications) may cause a single event upset (SEU) in either single or double nodes. Rather than masking, mitigation of an SEU is effectively achieved by recovering the correct value throughthe design of hardened latches. Using the polarity of the radiation-induced voltage pulse, a stacked design is proposed; this circuit permits to accomplish protection and SEU recovery at reduced overhead and so at substantially improved performance. The first proposed latch (RH-1) recovers all single node upsets and has an extremely low delay in its operation, because this latch propagates data to the output stage though only a transmission gate. The fast operation of RH-1 is utilized in the second latch (RH-2) proposed in this article. RH-2 consists of two RH-1 modules to guarantee that at least two nodes maintain the latched values under the occurrence of a double node upset. Simulation results are provided; they show that RH-1 (recovering all single node upsets and many double node upsets) has the best delay and power-delay-area product (PDAP, as combined metric) among all considered designs and the second-best area and dynamic power dissipation among the recovering schemes, and meanwhile RH-2 (recovering all double node upsets) has the best dynamic power dissipation and PDAP among all considered designs and the best area and delay among recovering schemes.