A 14 nm Embedded STT-MRAM CMOS Technology
D. Edelstein, Michael Rizzolo, Devika Sil, A. Dutta, J. DeBrosse, M.R. Wordeman, Abraham Arceo, I. C. Chu, J. Demarest, Eric R. J. Edwards, Eric R. Evarts, Jennifer Fullam, Arthur Gasasira, G. Hu, M. Iwatake, Richard Johnson, Veenadhar Katragadda, T. M. Levin, J. Li, Y. Liu, Colleen M. Long, T. Maffitt, S. McDermott, S. Mehta, V. Mehta, Dirk Metzler, Jaime Morillo, Yohei Nakamura, S. Nguyen, P. Nieves, Vijay S. Pai, R. Patlolla, R. Pujari, Richard G. Southwick, T. Standaert, O. van der Straten, Heng Wu, C.-C. Yang, D. Houssameddine, J. M. Slaughter, D. C. Worledge
Abstract
We present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. A novel integration supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 non-critical) and a single added electrode module. An advanced 400°C-compatible MTJ stack is read and written by innovative reference-cell sensing circuitry. We demonstrate digital functionality and write performance down to 4 ns, with companion parametric analysis for magnetoresistance, switching voltage, retention, and endurance cycling. Finally, we checked the 14 nm eMRAM hardware BEOL EM and TDDB at the critical levels, verifying good reliability after the embedding process.