Error Resolving in SRAM Emulated FPGA using CRC
A Aniruddh, E. Prabhu
Abstract
As there are increasing demand for communication system and storage systems in the modern world there can be errors such as soft errors during the data transmission between the communication system. Combining error correction and detection algorithms can give great dependability in data transmission and storage systems. The error detection and correction of the design is done using Ternary content addressable memory and a Cyclic redundancy check module from an SRAM. The scenario in this case is that when the data is commuted into the memory from any communication system its prone to soft errors over time or any external factors. The errors occurring must be reduced at any cost so the proposed system consists of the TCAM module that checks the memory with the given address in which the data is stored in the memory one after the other during the write operation of the memory. Once the write operation. A CRC module also adds to the system for the read operation for the error correction just in case of occurrence of error during the read operation. The designing of the module is done with Verilog HDL using ModelSim and the implementation of the schematics is done with Xilinx Vivado. This error detection and correction can help in detecting the error during the read and write operation ensuring the data integrity twice and there would be less chances for an error to occur.