Single and multiple switch fault‐tolerance capabilities in a hybrid five‐level inverter topology
Tushar Janarao Nistane, Lalit Kumar Sahu, Manik Jalhotra, Shivam Prakash Gautam
Abstract
The redundancy in switching states to generate different voltage levels is of great importance to incorporate fault‐tolerant features in multilevel inverters. However, this redundancy comes at the expense of high device count, which is paralleled with vulnerable characteristics of semiconductor devices, resulting in low reliability. About this concern, the present study introduces a novel fault‐tolerant topology to generate the five‐level output voltage. The proposed topology can tolerate open‐circuit failure, for single and multiple switches with the help of novel redundant leg architecture and short‐circuit condition is dealt with the fast fuses. The comparative study with recent literature is discussed, which reveals the superiority of the proposed topology, in terms of qualitative as well as quantitative parameters. Switching strategies are proposed under different single and multiple switch fault cases, which achieves self‐balancing of capacitor voltage. Thus, no complex control scheme is required. The simulation is performed in MATLAB/Simulink, and the feasibility of the proposed topology is validated using experimental results.