Efficient Implementation of Multiply Accumulate Operation Unit Using an Interlaced Partition Multiplier
N. Bhuvaneswary, S. Prabu, K. Tamilselvan, K. G. Parthiban
Abstract
A new strategy for quick multiplication of two numbers is introduced. Inputs are separated into segments, and one segment is replaced by two with zeros interlocking in each alternative segments. With zero carries between segments the product are computed, within the time needed to multiply the short partitions and add the partial sums. The multiplication of two numbers generated and adds that product to an accumulator by multiply accumulate operation (MAC unit). This operation is performed within the MAC unit. MAC is an advanced co-processor that plays a vital role in FFT, DFT, etc. The MAC unit is utilized for additional execution and its input is given to the proposed multiplier that provides a trivial speed increment over the array multiplier designs. This paper is utilized to design speed enhanced multiply Accumulate Unit by an Interlaced Partition Multiplier. This new multiplier design simulation is optimized with existing method.