A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference
Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent Carlton, May Wu
Abstract
This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.