A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout

Peter Deaville, Bonan Zhang, Naveen Verma

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)54 citationsDOI

Abstract

This paper presents a 128-kb in-memory computing (IMC) macro for fully row/column-parallel matrix-vector multiplication (MVM), implemented using a foundry MRAM in 22nm FD-SOI. Previous IMC in eNVM relied on RRAM with significantly higher resistance and resistance-state contrast than typical in foundry processes [1]–[3] or where parallelism was substantially reduced [4]. MRAM addresses distinct application requirements (e.g., temperature, radiation). This work advances previous MRAM IMC by improving area-normalized EDP by 60× over [5] and by employing a standard high-density bit cell without additional devices, as in [6]. This is achieved via a readout architecture that performs column-resistance boosting, with integrated auto-zeroing, and conductance-to-current sampling, to simultaneously feed four IMC columns to a single ADC for conversion to 6-b outputs (highest ADC precision among eNVM IMC designs).

Topics & Concepts

Magnetoresistive random-access memoryColumn (typography)Computer scienceStatic random-access memoryResistive random-access memoryParallel computingElectronic engineeringComputer hardwareElectrical engineeringEngineeringVoltageRandom access memoryTelecommunicationsFrame (networking)Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesAdvanced Data Storage Technologies