First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications
S. W. Chang, T.-H. Lu, Chenyi Yang, Chia-Nan Yeh, Min-Cheng Huang, Ching-Fan Meng, P.-J. Chen, Tin-Chun Chang, Yie-Jie Chang, Jhe-Wei Jhu, Tu Hong, Chu-Chu Ke, Xueqiang Yu, Wen-Hsiang Lu, Maughal Ahmed Ali Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, Fu-Kuo Hsueh, B.-Y. Chen, Hsuan-Lun Hu, C. T. Wu, Kuei-Huei Lin, W. C.-Y., Darsen D. Lu, Kuo-Hsing Kao, Y.-J. Lee, C.-L. Lin, K.-P. Huang, Kun‐Ming Chen, Yiming Li, Seiji Samukawa, T.-S. Chao, Guo‐Wei Huang, Wen-Fa Wu, Wen-Hsuan Lee, Jiun‐Yun Li, Jia‐Min Shieh, J.-H. Tarng, Y.-H. Wang, W.-K. Yeh
Abstract
In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-type IGZO and p-type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.