A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS
Taeryoung Seol, Se‐Hwan Lee, Geunha Kim, Samhwan Kim, Euiseong Kim, Seungyeob Baik, Jaeha Kung, Ji‐Woong Choi, Arup K. George, Junghyup Lee
Abstract
Precise current measurements underpin emerging applications such as photoplethysmography (PPG), electrochemical sensing, and fast-scan cyclic voltammetry (FSCV) [1–6], where the signal is a low-swing current that rides on a large, slow-varying baseline. Therefore, readout systems need a dynamic-range (DR) > 120dB, bandwidth (BW) >1 kHz, noise floor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$< 1\text{pA}_{\text{rms}}/\surd \text{Hz}$</tex> , and power <1 mW (Fig. 32.3.1 left). To widen DR, prior front-ends employ a prediction DAC [1], threshold-filter-based feedback-loop [2], and a Reset-Then-Open (RTO) DAC [3]. However, they widen the DR by sacrificing BW or power (Fig. 32.3.1 right). For instance, [1] employing a prediction DAC requires a power-hungry digital backend, while [2] with a threshold-filter-based feedback-loop is BW-limited (~20Hz). In contrast, [3] achieves wide-DR and BW, but consumes> 1 mW power. This paper presents a continuous-tirne <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> current-to-digital converter (IDC) that achieves wide-DR and BW at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu\mathrm{W}$</tex> power. To this end, it employs: 1) a 2nd-order <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{CT}-\Delta\Sigma$</tex> structure employing a highly linear pseudo-differential VCO quantizer, 2) an energy-efficient tri-level resistive DAC, and 3) a digital-intensive truncation-noise-shaped baseline-servo (TNS-BS) loop that extends the DR at low power and area.