First Demonstration of Deeply Scaled 2T0C DRAM With Record Data Retention and Fast Write Speed
Shenwu Zhu, Qianlan Hu, Qijun Li, Shiwei Yan, Honggang Liu, Ranhui Liu, Yanqing Wu
Abstract
In this work, the first pitch scaling of 2T0C dynamic random-access memory (DRAM) based on indium-tin-oxide (ITO) transistors has been successfully fabricated, achieving a record-low contact length of 20 nm and channel length of 10 nm. The deeply scaled 2T0C DRAM demonstrates multi-level operation with an ultra-fast write speed of 10 ns, facilitated by a high on-state current. Furthermore, it features an outstanding data retention time exceeding 3000 s, attributed to its low off-state leakage current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.3 \times {10}^{-20}$ </tex-math></inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m. This work highlights the tremendous potential of oxide semiconductor-based 2T0C DRAM for future high-density memory applications.