An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit
Jiacong Sun, Hao Guo, Geng Li, Hailong Jiao
Abstract
Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \mu \text{m}$ </tex-math></inline-formula> 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain.