Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
Longjie Zhong, Shubin Liu, Donglai Xu
Abstract
MEMS capacitive accelerometer for the Internet of things applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout structure instead of charge control readout structure is preferred for low cost. However, the voltage control readout structure suffers from low power efficiency (in terms of <i>FoM</i>) due to significant parasitic-capacitance-induced noise. In this paper, the correlated double amplifying (CDA) technique is proposed to reduce the noise of the voltage control readout circuit with high power efficiency. Although, traditional correlated double sampling (CDS) technique can also be used in readout circuit to reduce the parasitic-capacitance-induced noise, it sacrifices driving ability and bandwidth of the readout circuit while CDA does not. The CDA technique adopts correlated amplifying to reduced noise without significant increase of power consumption. Thus, CDA technique leads to higher power efficiency. The CDA technique is demonstrated in a fully-differential readout circuit fabricated in a 0.18um CMOS process and tested with a sensing element from a commercial MEMS accelerometer. The measurement results show that noise floor of the readout circuit is 0.5<i>aF</i>/√<i>Hz</i> and the noise floor of the whole system is 112<i>ug</i>/√<i>Hz</i>, with a power consumption of 139μW and a bandwidth of 12.5kHz. The full input range is ±4g, a <i>FoM</i><sub>1</sub> of 80<i>pJ</i> and a <i>FoM</i><sub>2</sub> of 254<i>uW</i> ∙ <i>ug</i>/<i>Hz</i> are achieved.