7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET
Marco Cusmai, Noam Familia, Elad Kuperberg, Mohammad Nashash, Dovid Gottesman, D. Sriram Kumar, Zvi Marcus, Yeshayahu Horwitz, Sagi Zalcman, Jihwan Kim, Sandipan Kundu, Ilia Radashkevich, Yoav Segal, Dror Lazar, Udi Virobnik, Mike Peng Li, Ariel Cohen
Abstract
As the 800Gb/1.6Tb Ethernet ecosystem develops, a need for single-lane interface speeds beyond 200Gb/s arises. With the first 224Gb/s transmitter and receiver architectures demonstrated in [1] and [2], required energy efficiency per bit and flexibility of silicon proven 112Gb/s designs [3] –[5] have yet to be reached. Doubling the data-rate puts stringent challenges on the circuit design due to the extra analog bandwidth required, together with the necessary improvement of both random and deterministic jitter performance. This article describes a 224Gb/s transmitter based on a 7b DAC driver (4b binary, 3b thermometer-coded) with 9-tap FFE capable of both PAM-4 and PAM-6 modulations. The architecture and design are optimized for power efficiency at all supported data rates.