Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values <i/> <i/>
Yanna Luo, Lei Cao, Qingzhu Zhang, Yu Cao, Zhaohao Zhang, Jiaxin Yao, Gangping Yan, Xuexiang Zhang, Weizhuo Gan, Jiali Huo, Haoqing Xu, Guo‐Liang Tian, Weihai Bu, Yongqin Wu, Zhenhua Wu, Huaxiang Yin
Abstract
Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pds}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pud}}$ </tex-math></inline-formula> ) and from access (AX) devices to bit-lines (BLs) ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> and increased <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pud}}$ </tex-math></inline-formula> is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> in the buried-BL scheme is proven to have higher WM, as well as lower WT. The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.