Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni
Abstract
One of the most critical aspects of integrating loosely-coupled accelerators in heterogeneous SoC architectures is orchestrating their interactions with the memory hierarchy, especially in terms of navigating the various cache-coherence options: from accelerators accessing off-chip memory directly, bypassing the cache hierarchy, to accelerators having their own private cache. By running real-size applications on FPGA-based prototypes of many-accelerator multi-core SoCs, we show that the best cache-coherence mode for a given accelerator varies at runtime, depending on the accelerator’s characteristics, the workload size, and the overall SoC status.
Topics & Concepts
Computer scienceEmbedded systemWorkloadCoherence (philosophical gambling strategy)Cache coherenceMode (computer interface)Computer architectureOrchestrationKey (lock)Operating systemGeneral purposeCacheVMEbusComputer hardwareCPU cacheRandom access memorySpatial coherenceParallel Computing and Optimization TechniquesFerroelectric and Negative Capacitance DevicesAdvanced Memory and Neural Computing