Efficient and High-Speed CGRA Accelerator for Cryptographic Applications
Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima
Abstract
Efficient cryptographic hardware architectures must exhibit both high performance and flexibility to effectively meet the diverse demands of data security in multi-domain applications. However, current research faces challenges in achieving a balance between high processing speed and flexibility, leading to low hardware efficiency and limitations in applicability. Therefore, this paper proposes the ultra-efficient crypto-processor (UECP), a coarse-grained reconfigurable arrays (CGRA) accelerator designed to support various cryptographic algorithms, offering excellent performance and hardware efficiency. To significantly enhance performance and configuration efficiency, the UECP implements two optimal techniques: a 4x4 pipelined processing element array (PEA) and an effective configurable arithmetic logic unit (C-ALU). The performance evaluation of the UECP on the Xilinx ZCU102 FPGA at the system-on-chip level demonstrates a throughput ranging from 1.45 to 4.35 Gbps, power consumption of 0.357 W, and remarkable energy efficiency of 12.19 Gbps/W. The UECP on FPGA outperforms modern embedded CPUs such as ARM Cortex A53 and ARM Cortex A57 by 6.23-24.1 $\times$ in various algorithm computations. Moreover, when compared to current low-flexibility FPGA-based designs, the flexible UECP demonstrates a throughput superiority of 1.58- 10.71$\times$. Finally, the ASIC synthesis comparison results show that the UECP outperforms related works with 7.16-22$\times$ higher throughput, 7.92-22.5$\times$ better area efficiency, and 1.76-15.36$\times$ superior energy delay products (EDP).