All‐Solid‐State Electrolyte‐Gated Synaptic Transistor Array for Deep Learning Hardware Accelerators
Zezhong Yin, Dandan Hao, Ranran Ci, Guangtan Miao, Yuhui Wang, Dong Yao, Ao Liu, Fukai Shan
Abstract
Abstract In‐memory computing architectures based on artificial synaptic arrays offer higher computing efficiency than traditional hardware in deep learning applications. However, the core devices within the array must be capable of achieving high linearity and symmetric conductance programming with minimal variability. In this report, solid‐state electrolyte thin films of lithium and fluorine co‐doped ZrO 2 (F:ZrLiO x ) are prepared by the sol–gel method, and electrolyte‐gated synaptic transistors (EGSTs) based on In 2 O 3 /F:ZrLiO x are fabricated. The F:ZrLiO x EGSTs demonstrate excellent synaptic performance, and show potential for large‐scale integration with silicon‐based circuits. To further verify the potential of F:ZrLiO x EGSTs for application in deep learning, a 10 × 10 synaptic transistor array is fabricated using F:ZrLiOx EGSTs. This array exhibits a large dynamic range (G max /G min = 105.71), high linearity (0.38/−0.68), and high stability (10 3 cycles) in the conductance updating process. It can also perform precise convolution operations for feature extraction from input images. As a hardware accelerator for convolutional neural networks (CNNs), the F:ZrLiO x EGST array attains a high image recognition accuracy of 96.3% based on the CIFAR‐10 dataset. These results illustrate the technological potential of the F:ZrLiO x EGST array as a cost‐efficient and high‐performance hardware accelerator for neural networks in deep learning.