Design of half adder using integrated leakage power reduction techniques
Hima Bindu Katikala, T. P. Santosh Kumar, Bhimavarapu Manideep Reddy, Bandireddy V.V.Pavan Kumar, G. Ramana Murthy, Saurav Dixit
Topics & Concepts
CMOSSubthreshold conductionLeakage (economics)Power gatingLeakage powerTransistorAdderElectrical engineeringElectronic engineeringElectronic circuitIntegrated circuitScalingComputer scienceVoltageEngineeringMathematicsMacroeconomicsGeometryEconomicsLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit DesignAnalog and Mixed-Signal Circuit Design