Monolayer <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline" overflow="scroll"><mml:msub><mml:mi>WSi</mml:mi><mml:mn>2</mml:mn></mml:msub><mml:msub><mml:mrow><mml:mrow><mml:mi mathvariant="normal">N</mml:mi></mml:mrow></mml:mrow><mml:mn>4</mml:mn></mml:msub></mml:math>: A promising channel material for sub-5-nm-gate homogeneous CMOS devices

Abstract

Complementary metal oxide semiconductor (CMOS) devices require both n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but achieving both types that meet the requirements of the International Technology Roadmap for Semiconductors (ITRS) at ultrashort gate lengths is a challenge. Recently synthesized two-dimensional crystal ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ exhibits high theoretical hole and electron carrier mobilities. In this study, we investigate the performance limits of double-gated (DG) monolayer (ML) ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ MOSFETs with sub-5-nm gate lengths using first-principles density-functional theory and the nonequilibrium Green's function method. Our results show that both the n-type and p-type DG ML ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ MOSFETs can meet the requirements of ITRS 2013 for high-performance (HP) applications at the 2028 technology node, even when the gate length is scaled to 3 nm. For low-power applications, the scaling limits for the gate lengths of the n-type and p-type DG ML ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ MOSFETs are 4 and 5 nm, respectively. Importantly, the on-state currents of the n-type and p-type HP DG ML ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ MOSFETs are highly symmetric, highlighting the potential of ML ${\mathrm{WSi}}_{2}{\mathrm{N}}_{4}$ as a promising material for building next-generation CMOS devices, especially for HP applications.

Topics & Concepts