A 94.6 to 105.2GHz CMOS Power Amplifier Achieving 17dBm P<sub>sat</sub>, 12.5dBm OP<sub>1dB</sub> and 11.5% PAE with a Digital Power Detection Loop
Liangming Lian, Yuxin Zhang, Yiqian Shan, Yuan Liang, Jin Wen, Ke Yang
Abstract
A complementary metal oxide semiconductor (CMOS) 100GHz CMOS power amplifier (PA) with a digital power detection loop is reported attaining high saturated output power and enhanced power-added efficiency. In order to coherently combine multiple CMOS power transistors within a compact area, a two-dimension distributed transmission line integrated with compact transformers is introduced. Each PA unit-cell is designed in a way such that multiple common source amplification stages are coupled by transformers, and the overall 8-path PA unitcell are combined by transmission line. Moreover, a digital power detection loop is introduced for adaptive biasing realizing high power efficiency during power back-off, such that the PA quiescent power is reduced along with the output power. An 8-path power-combined CMOS PA was realized in a standard 28nm bulk CMOS technology. Simulation results have shown a saturated output power P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> of 17dBm, PAE of 11.5%, OP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> of 12.5dBm, and up to 40% power efficiency enhancement during power back-off from 95.6 to 102.5GHz.