A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density
A. Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzmán, Chang Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, O. Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen V. Prabhu, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, B. Pathak, Pranav Kalavade
Abstract
Successful deployment of multiple generations of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\mathsf{b}/\mathsf{cell}$</tex> (QLC) floating-gate 3D-NAND technology has paved the way for the industry-wide adoption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathsf{QLC} [1-4]$</tex> . The transition to 5b/cell (PLC) will be another steppingstone to accelerating bit density growth and expanding Flash storage to wider markets, where a lower cost at a reasonable performance is the paramount requirement.