15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm<sup>2</sup> Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C
Yi‐Cheng Huang, Shanni Liu, H. W. Chen, Hsin-Chang Feng, Chih-Feng Li, C T Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
Abstract
Low-power wireless MCU devices for intelligent IoT applications are one of the key drivers for embedded non-volatile memory (eNVM) for technology nodes of 2xnm and beyond; in addition to high-performance advanced CMOS processes with excellent RF/analog devices, there is a need for high read throughput high-density embedded non-volatile memory to store CPU code as well as neural-network models for energy-efficient data-centric machine-learning edge computing. For this purpose, fully logic-compatible TMO-based resistive RAM (RRAM) is a promising candidate [1–3]. In this work, a 32Mb RRAM macro with $0.0249 \mu m^{2}$ bit cells is implemented using a 12nm ultra-low power FinFET technology. Several design solutions are also proposed to address key challenges, including a write-assist scheme to achieve high write endurance and data retention and a pipeline-read scheme for high read throughput. Silicon measurements show 10,000 write-cycle endurance, 10-year retention at $105^{\circ}\mathrm{C}$, and a 3.2GB/s read throughput.