A 0. 25μm700V BCD Technology with Ultra-low Specific On-resistance SJ-LDMOS
Nailong He, Sen Zhang, Xuhan Zhu, Xuchao Li, Hao Wang, Wentong Zhang
Abstract
In this paper, a 0.25 μm 700 V Bipolar-CMOSDMOS (BCD) process platform is reported, which integrates the super junction lateral double-diffused metal-oxide semiconductor (SJ-LDMOS) with ultra-low specific on-resistance Ron,sp. The SJ-LDMOS features the SJ pillars in the bulk of the drift region, introducing a low resistance current path in the on-state and decreasing the Ron,sp. By optimizing the charge balance among the N-drift region, PN pillars and P-substrate, the proposed SJ-LDMOS can be used at 500 V, 650 V and 700 V voltage levels with the experimental breakdown voltage VB of 605 V, 745 V and 790 V. The corresponding Ron,sp is 3.3 Ω·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 5.8 ·.mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 7.1 Ω·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The measured R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is 45.5% lower than the theoretical limit of the triple RESURF technology under the same V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> . This SJ-based 700V BCD technology also provides other variable integrated devices: 700 V nJFET; 30 V / 15 V / 7.5 V CMOS; 20 V NPN and PNP; and poly resistor.