Litcius/Paper detail

A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror

Kai Yu, Jiyang Chen, Sizhen Li, Mo Huang

2023IEEE Transactions on Circuits & Systems II Express Briefs14 citationsDOI

Abstract

This brief proposes a nano-watt self-biased CMOS voltage reference (SBCVR) with a quasi self-cascode current mirror (QSCCM) for better line sensitivity (LS) and power supply rejection ratio (PSRR). A self-cascode MOSFET (SCM) and a cascode structure are combined as the QSCCM to reduce the variations of bias current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(I_{\mathrm{ B}})$ </tex-math></inline-formula> through the QSCCM, comparing to conventional ones. Then, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ B}}$ </tex-math></inline-formula> is fed into an active load to acquire a more stable reference voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ REF}})$ </tex-math></inline-formula> against the supply voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ DD}})$ </tex-math></inline-formula> without using any additional native devices, amplifiers, pre-regulation circuits, and DIBL compensation circuits. The proposed SBCVR with the QSCCM is fabricated in a standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 \mu \text{m}$ </tex-math></inline-formula> CMOS process, while 22 chip samples are measured. The results show that the average LS is 0.011%/V when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ DD}}$ </tex-math></inline-formula> varies from 0.8 V to 1.8 V. The average PSRR are −76dB, −53 dB, and −59 dB at 10Hz, 1kHz, and 1MHz respectively. Moreover, it can produce a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ REF}}$ </tex-math></inline-formula> of 293 mV and consume a supply current of 1.95 nA <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm{ DD}}=$ </tex-math></inline-formula> 1V) at 27 °C. The average temperature coefficient (TC) is 66.1 ppm/°C without trimming in the temperature range from −40 °C to 85 °C, while the total area is only 0.004 mm 2.

Topics & Concepts

NotationCMOSPower supply rejection ratioTopology (electrical circuits)Electrical engineeringBiasingAmplifierPhysicsMathematicsVoltageArithmeticEngineeringAnalog and Mixed-Signal Circuit DesignAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devices