A DC–<i>Ka</i>-Band 7-Bit Passive Attenuator With Capacitive-Compensation-Based Bandwidth Extension Technique in 55-nm CMOS
Zijiang Zhang, Nayu Li, Huiyan Gao, Min Li, Shaogang Wang, Yen‐Cheng Kuan, Chunyi Song, Xiaopeng Yu, Qun Jane Gu, Zhiwei Xu
Abstract
This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The π-type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area and consumes negligible power.