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A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

Kyoung-Jun Moon, Dong‐Ryeol Oh, Young-Hyo Park, Kyunghoon Lee, Sun‐Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyochul Shin, Young‐Jae Cho, Michael Choi, Jong-Shin Shin

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)19 citationsDOI

Abstract

A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Walden</inf> of 305fJ/c-s.

Topics & Concepts

SkewCalibrationComputer scienceChannel (broadcasting)Electronic engineeringSuccessive approximation ADCPower consumptionNyquist–Shannon sampling theoremPower (physics)VoltageElectrical engineeringComparatorPhysicsEngineeringTelecommunicationsQuantum mechanicsAnalog and Mixed-Signal Circuit DesignCCD and CMOS Imaging SensorsAdvancements in Semiconductor Devices and Circuit Design
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET | Litcius