A 5–11 GHz 8-bit Precision Passive True-Time Delay in 65-nm CMOS Technology
Jeong-Moon Song, Jung‐Dong Park
Abstract
In this paper, we present an 8-bit precision passive true-time delay (TTD) operating at 5–11 GHz in 65-nm CMOS technology. To achieve a precision time delay control, the 8-bit TTD employs a 4-bit time delay circuitry that utilizes two <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> delay networks in parallel to reduce the effects of the nonideal lumped components and layout imbalance of a conventional TTD. To design an 8-bit TTD, a 4-bit TTD with conventional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> networks was also used for the 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> bit to the 8 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> bit (MSB) time-delay for coarse delay control. The implemented 8-bit TTD circuit achieved a minimum delay of 1.56 ps and a maximum delay of 400 ps, demonstrating the smallest loss per delay among the recently reported state-of-the-art silicon-based TTDs without dissipating any DC power and with a chip area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.76\times 1.01$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .