A Fractional-<i>N</i> Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
Gaofeng Jin, Fei Feng, Wen Chen, Yiyang Shu, Xun Luo, Xiang Gao
Abstract
This article presents a 3.3–4.5-GHz fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> analog sampling phase-locked loop (SPLL). A merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) allows phase error detection as well as quantization noise (QN) cancellation in a single ramp generation, which reduces the source of noise and nonlinearity. A modified multimodulus divider (MMDIV) with two phase retimers reduces the required CSDTC-SPD linear range and decreases the noise from the CSDTC-SPD. To verify the principle, a prototype SPLL was implemented and fabricated in a conventional 40-nm CMOS technology. The measured results show the merits of an rms jitter of 203 fs with 2.4-mW power, which leads to a phase-locked loop (PLL) figure of merit (FoM) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 250 dB.