An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration
Hongshuai Zhang, Yan Zhu, Chi‐Hang Chan, Rui P. Martins
Abstract
This article presents an inherent gain error-tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the pipeline, realizing an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> -0 (2-0) multistage NS sigma–delta (MASH). The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> th order from the first stage shapes not only the quantization error and comparator noise but also the interstage gain and nonlinearity error, which greatly relaxes the gain accuracy constraint in the conventional pipelined architecture. In addition to gain, a code-counter-based (CCB) background offset calibration is introduced to mitigate the interstage offset with low cost. The prototype further adopts partial interleaving in the first stage for high speed while sharing the integration capacitors in the feed-forward (FF) structure for a compact area. The 2-0 MASH runs at 400 MS/s and achieves 25-MHz bandwidth with 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> OSR, consuming 1.26-mW power from a 1-V supply. Within a gain error range of −16% to +12%, the SNDR of the ADC deviates less than 3 dB from the nominal 75-dB SNDR. Fabricated in a 28-nm CMOS process, it exhibits a 178-dB Schreier figure of merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ).