Record 7(N)+7(P) Multiple V<sub>T</sub>s Demonstration on GAA Si Nanosheet n/pFETs using WFM-Less Direct Interfacial La/Al-Dipole Technique
Jiaxin Yao, Yanzhao Wei, Shuai Yang, Hong Yang, Gaobo Xu, Yadong Zhang, Lei Cao, Xuexiang Zhang, Qianqian Liu, Zhenhua Wu, Huaxiang Yin, Qingzhu Zhang, Junfeng Li, Jun Luo
Abstract
In this paper, for the first time, we have realized record 7(N)+7(P) multiple threshold voltages (Multi-V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> s) on horizontal gate-all-around (GAA) Si nanosheet (SiNS) n/pFETs using work-function-metal-less (WFM-less) direct interfacial La/Al-dipole technique, regardless of the sheet-to-sheet spacing (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sus</inf> ) pinch-off in stacked channels. Owning to higher dipole intensity in ultra-thin high-k dielectric (HK) films obtained by ALD in-situ direct dual dielectric La-/Al-dipole (D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ) control between adjacent NSs, both nFETs and pFETs have achieved 7 V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> s (1 RVT, 3 HVT and 3 LVT) with good uniformity and discrimination even in WFM-less gate stack. The maximum V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> tuning ranges reach 1105 mV/873 mV and the minimum discriminable ΔV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> over 83mV/76mV for n/pFETs, respectively, exhibiting great multi-V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> s application advantages for future high performance and low power GAA SiNS CMOS process.