An Analog, Low-Power Threshold Classifier tested on a Bank Note Authentication Dataset
Vassilis Alimisis, Georgios Gennis, Errikos Tsouvalas, Christos Dimas, Paul P. Sotiriadis
Abstract
Bank note authentication devices are used widely in many large scale stores and companies. Their main focus is to accurately detect all the forged bank notes regardless of a few false alarms on genuine ones. In this work, a low power (210nW), area efficient (0.057mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), analog threshold classifier is proposed to operate as a bank note authentication circuit. The architecture consists of bump and Winner-Take-All circuits. A real-world bank note authentication dataset is used to confirm the proper operation of the proposed classifier, via post-layout simulations in a TSMC 90nm CMOS process, using the Cadence IC Suite. The achieved recall (91.0%) indicates that the classifier is capable of detecting forged bank notes successfully.