A Wideband Low RMS Phase/Gain Error mm-Wave Phase Shifter in 22-nm CMOS FDSOI
Mohammad Ghaedi Bardeh, Jierui Fu, Navid Naseh, Jeyanandh Paramesh, Kamran Entesari
Abstract
A 5-bit low-power and compact active mm-wave phase shifter (PS) with low rms phase/gain error is implemented in 22-nm CMOS fully depleted silicon on insulator (FDSOI) technology for 5G multi-input multi-output (MIMO) phased arrays. The proposed phase shifter uses a gain-boosted two-stage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> poly-phase filter (PPF), which maintains reasonable phase accuracy features while compensating for the gain response. The system uses a reactance invariant cascode vector modulator (VM), which results in constant loading effect for quadrature network, therefore improving rms phase/gain error. The phase shifter shows measured rms phase error of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$< 4^{\circ }$ </tex-math></inline-formula> at 24–36 GHz. The measured mean gain is from −8.2 to −5 dB at 24–36 GHz, and the rms gain error is < 0.6 dB at 24–36 GHz. The total power consumption of the proposed phase shifter is 7.2 mW, and the chip area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$612\times 953\,\,\mu \text{m}$ </tex-math></inline-formula> including pads.