A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications

Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po‐Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li

2020IEEE Journal of Solid-State Circuits34 citationsDOI

Abstract

A 135-Mb 0.021-μm 2 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.

Topics & Concepts

Static random-access memoryExtreme ultraviolet lithographyCMOSChannel (broadcasting)Charge sharingOptoelectronicsElectrical engineeringCoupling (piping)Materials scienceVoltageComputer scienceEngineeringMetallurgySemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-<i>V</i> <sub>MIN</sub> Applications

Abstract

Topics & Concepts