Design and Performance Benchmarking of 8T SRAM Cell using Dynamic Feedback Control
Jay Kaushik, Somesh Kumar
Abstract
Random-access memory (RAM) is an information storage device commonly used for storing run-time variables and instructions in micro controllers and processing units. The demand for portable devices has led to a need for ultra-low power consumption in electronic circuits. This has resulted in the development of new circuit topologies and optimization techniques that aim to minimize power consumption while maintaining performance and functionality. In this work, Dynamic feedback control (DFC) technique is applied to 8T static random-access memory (SRAM) to reduce power consumption while maintaining performance, and the performance benchmarking is done on 22nm technology nodes at different process corners i.e. SS, FF, SF, FS. From the results, it is seen that PDP has decreased by 54% in write 1 power when the comparison is done between 8T SRAM Cell without DFC and 8T SRAM Cell with DFC. From this analysis, we can say that 8T SRAM cell with DFC consumes less power and delay as compared to conventional 8T SRAM cell.