2D Materials in Logic Technology: Power Efficiency and Scalability in 2DM-MBC CFET
S. H. Shin, Dong‐Ho Kang, Hoon Hahn Yoon, Jin Young Park, Minuk Song, Hyeonchang Son, Daewon Ha, Hyeon‐Jin Shin
Abstract
Sustaining digital evolution demands high-performance logic technology with a high density, high speed, and low power consumption to process large data sets efficiently. Power consumption remains a critical issue in miniaturized logic devices, impacting reliability, device lifetime, and circuit scalability. This review explores key parameters in logic FETs to manage power consumption, examining advancements in both unit and array structures. We provide a detailed overview of the development history of logic FETs, highlighting structural innovations and challenges for achieving low power consumption. Furthermore, we investigate the state-of-the-art potential of 2D materials (2DMs) in 3D-stacked structures, such as 2DM-MBC CFETs, emphasizing their benefits for ultralow power devices. Finally, we address the current progress and challenges in developing 2DM NMOS and PMOS for CFET industrialization and present an outlook on advancing 2DM-MBC CFET technology to meet the demands of future logic technology.