Litcius/Paper detail

A fully integrated D-band direct-conversion I/Q transmitter and receiver chipset in SiGe BiCMOS technology

S.H. Carpenter, Herbert Zirath, Zhongxia Simon He, Mingquan Bao

2021Journal of Communications and Networks22 citationsDOIOpen Access PDF

Abstract

This paper presents design and characterization of single-chip 110–170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and ×6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3dB RF bandwidth of 28 GHz from 112–140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm×1.1 mm.

Topics & Concepts

ChipsetDirect-conversion receiverTransmitterAmplifierElectrical engineeringRadio receiver designFrequency multiplierBiCMOSNoise figureBasebandWidebandSuperheterodyne receiverGilbert cellBandwidth (computing)Phase noiseCMOSDemodulationVoltage-controlled oscillatorChipRadio frequencyComputer scienceTelecommunicationsEngineeringTransistorDetectorVoltageChannel (broadcasting)Radio Frequency Integrated Circuit DesignMicrowave Engineering and WaveguidesElectromagnetic Compatibility and Noise Suppression