HDL Environment for the Synthesis of 2-Dimensional and 3- Dimensional Network on Chip Mesh Router Architecture
Shweta Kumari, Kapil Rajput, Gurwinder Singh, Arpit Jain, Savya Sachi, Manika Manwal
Abstract
Application specific Network on Chip (NoC) designs are quickly becoming the technology of choice for solving the problem of multiprocessor system architecture. Broadband, interposes communication, deadlock avoidance, port bandwidth, router architecture, and bespoke NoCs may all be improved by modelling and simulation of multilayer network structures and synthesis. Topology-based organization of 2D and 3D routers allows for the construction and laDyout of NoCs. The articles compare and contrast the design and analysis of two-dimensional and three-dimensional network-on-chip routers for setting up mesh topological nodes in a network. Xilinx 14.2 is used to execute the code. The most recent version of modalism, 10.0 student edition, is used to functionally mimic the program and modules. The experimental work and thorough testing on the Virtex-5 FPGA confirm the chip design.