A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays

Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)50 citationsDOI

Abstract

This paper presents an ADC-free compute-in-memory (CIM) RRAM-based macro, exploiting the fully analog intra-/inter-array computation. The main contributions include: 1) a lightweight input-encoding scheme based on pulse-width modulation (PWM), which improves the compute throughput by ~7 times; 2) a fully analog data processing manner between sub-arrays without explicit ADCs, which does not introduce quantization loss and saves the power by a factor of 11.6. The 40nm prototype chip with TSMC RRAM achieves energy efficiency of 421.53 TOPS/W and compute efficiency of 360 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (normalized to binary operation) at 100MHz.

Topics & Concepts

Quantization (signal processing)Resistive random-access memoryPulse-width modulationComputer scienceMacroBinary numberModulation (music)ConvertersChipEncoding (memory)Electronic engineeringComputer hardwareThroughputComputationElectrical engineeringAlgorithmVoltagePhysicsArithmeticEngineeringArtificial intelligenceTelecommunicationsMathematicsWirelessProgramming languageAcousticsAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesSemiconductor materials and devices