Design of 16-Bit and 32-Bit Approximate Full Adder Using Majority Logic
Poojitha Lagidi, Aenugula Iswarya, Gangarapu Rajesh, A. S. Keerthi Nayani
Abstract
With the increasing technology rises the need of increase in storage. An adder is best known for performing arithmetic operations that takes n-input and produces two outputs i.e., sum and carry out. This paper proposes a 16-bit and 32-bit Approximate Full Adder based on Majority Logic. Use of approximate computing increases the storage capacity. The Majority Logic has become a basic gate for most of advanced circuits. We are using a majority logic that is composed with simple AND gates. Hence, with the use of Majority Logic and approximate computing, the delay and area consumed by the components can be reduced. The proposed Adder is designed with the one-bit approximate full adder based on the majority logic. A commendable reduce in delay by 77% and 82% is obtained for 16-bit and 32-bit design respectively and utilized area by the components is decreased by 54.8% and 51.5% for 16-bit and 32-bit design respectively when compared to existing designs.