On the Channel Percolation in Ferroelectric FET Towards Proper Analog States Engineering
Kai Ni, Simon Thomann, Om Prakash, Zijian Zhao, Shan Deng, Hussam Amrouch
Abstract
Harnessing its analog threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> ) states, ferroelectric FET (FeFET) has found wide applications as multi-level cells and synaptic weight cells for in-memory computing. However, the origin of analog <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V$</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> states are not well understood. Moreover, channel percolation is predicted, which could significantly limit the number of analog states due to the abrupt V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> change during percolation. In this work, through extensive theoretical investigations using combined TCAD and resistor network simulations, we found that: i) channel percolation is not universally present in FeFETs though with the random spatial fluctuation of the polarization states; ii) the resistor network model, when applied to study percolation in FeFETs, neglects the critical carrier diffusion in the channel, and hence neighbor interactions; iii) channel percolation only happens when the domain size is larger than the carrier diffusion length such that neighbor interaction is suppressed. These insights provide an important guideline for future FeFET analog states engineering.