Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier
Tae-Bin Kim, Hyunjin Kim, Kee-Won Kwon
Abstract
This brief proposes fast and efficient offset compensation for a DRAM bit-line sense amplifier. Precharging the sense amplifier under the same conditions as the initial offset compensation eliminates the deterministic offset leaving a small stochastic offset to be cured during the compensation step. The compensated offset is maintained throughout the subsequent charge sharing and sensing periods by keeping the noise environment constant as a compensation step to prevent an additional offset from being introduced after compensation. Fast and reliable offset compensation is confirmed by yield analysis in 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 288 DRAM cell array using extensive Monte Carlo simulation. Even when the offset compensation time is shortened to 2 ns, no yield drop is expected while with conventional amplifiers a sensing failure is estimated at 47.5%. An additional 1 ns reduction in charge sharing time is possible if a careful power delivery network is provided with the proposed sense amplifier.