28.1 A Distortion-Free VCO-Based Sensor-to-Digital Front-End Achieving 178.9dB FoM and 128dB SFDR with a Calibration-Free Differential Pulse-Code Modulation Technique
Jiannan Huang, Patrick P. Mercier
Abstract
Motion and stimulation artifacts encountered in wearable sensors present difficult dynamic range (DR) and linearity challenges: AFEs need to be able to resolve μV-level signals in the presence of artifacts up to 100s of mV in amplitude while maintaining linearity without saturation, such that the signal of interest can be readily recovered during post-processing. Since it is not possible to build an amplifier with appreciable gain and linearity for >100mV inputs under <; 1V SoC-compatible supply, most high-DR AFEs instead incorporate an LNA into a ΔΣ-based ADC-direct architecture [1-3]. However, as many emerging wearable devices desire single-chip integration in scaled CMOS for size and digital performance considerations, conventional ΔΣMs, which rely on voltage-domain building blocks, suffer from reduced intrinsic gain and headroom. Instead, time-domain quantization through VCO-based AFEs benefits from scaled CMOS and offers intrinsic 1st-order noise shaping. However, the non-linear V-F conversion of conventional VCO-based AFEs makes achieving a large and linear DR difficult [1]. To address this, [3] adopts a differential pulse code modulation (DPCM) technique that enables the VCO to process only a small prediction error, VERR, by subtracting from VIN a digital predictor value fed through a DAC (Fig. 28.1.1 top). Maximal linearity would be achieved if the predictor was perfect, resulting in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ERR</sub> ≈ 0; however, this requires a high-performance and power-expensive DAC. Therefore, [3] truncates the predictor's output, reducing the DAC requirements to 9b, but adding truncation error, ET. If the gain of paths P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are made equal, which is enforced in [3] via a gain error calibration (GEC) circuit, E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> will ideally cancel at the output. However, it is not possible to achieve perfect E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> cancellation, and any residual ET will degrade SQNR, limiting the extent to which truncation can be used to relax the DAC's resolution. In addition, GEC itself introduces power overhead.