A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui P. Martins, Pui‐In Mak
Abstract
This article reports a high-density 3T1C single-finger (SF) embedded dynamic random access memory (eDRAM) compute-in-memory (CIM) macro. It features several techniques that enhance the memory density, the energy efficiency, and the throughput density, namely: 1) a high-density 3T1C SF-eDRAM cell with low-leakage retention (LLR) to improve the memory density significantly with a competitive retention time; 2) a bit-wise input-sparsity-aware (ISA) p-source input strategy for SF-eDRAM cell to save the energy dissipation of the eDRAM array; 3) a bit-significance-aware (BSA) analog-to-digital converter (ADC) to reduce the energy dissipation; and 4) a kernel-wise weight-update-and-refresh (KWUR) to improve the kernel-wise CIM utilization rate and the eDRAM-CIM macro throughput during weight update/refresh. The proposed 128-kb SF-eDRAM CIM macro prototyped in 28-nm CMOS exhibits a memory density of 2.28 Mb/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> , reaches a peak throughput density of 18.7 TOPS/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> , and a peak energy efficiency of 234.6 TOPS/W performing 8b operations.